The present invention relates to a semiconductor device and, more particularly, to a data output circuit of the semiconductor device.
In a conventional semiconductor device of the kind to which the present invention relates, an inverter is utilized as a data output circuit.
A typical example of such a conventional data output circuit is shown in FIG. 1. In the figure, IN is a data input node, OUT is a data output node, Q.sub.P is a P-channel MOS field effect transistor (hereinafter referred to as "FET"), Q.sub.N is an N-channel MOSFET, V.sub.CC is a power source line, and GND is ground line. In such a data output circuit, the P-channel MOSFET Q.sub.P turns OFF and the N-channel MOSFET Q.sub.N turns ON when the potential of the data input node IN becomes a high level (hereinafter referred to as "H") and, upon the data output node OUT being grounded through the N-channel MOSFET Q.sub.N, this output node OUT turns to the ground level, that is, 0 V. On the other hand, when the potential of the data input node IN becomes a low level (hereinafter referred to as "L"), the P-channel MOSFET Q.sub.P turns ON and the N-channel MOSFET Q.sub.N turns OFF and, upon the data output node OUT being connected to the power source line V.sub.CC through the P-channel MOSFET Q.sub.P, the output node OUT turns to the level of the power source level (hereinafter referred to as "V.sub.CC level"). Thus, in such conventional data output circuit, the inverter which is constituted by the P-channel MOSFET and the N-channel MOSFET outputs 0 V level and V.sub.CC level with respect to one bit input.
In the conventional semiconductor device as explained above, it is necessary to provide one output node (that is, one output wiring) for every one-bit input so that, in order to be able to transfer a number of data internally in a chip, an area for the output wirings in the chip has to be inevitably large, which is a disadvantage in achieving a high integration of the semiconductor integrated circuit device.